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− | <h1 style="font-size:2.3rem;text-align:center">The AND gate is a basic digital logic gate that implements logical conjunction. A HIGH output (1) results only if all the inputs to the AND gate are HIGH (1)</h1> | + | <h1 style="font-size:2.3rem;text-align:center">"The AND gate is a basic digital logic gate that implements logical conjunction. A HIGH output (1) results only if all the inputs to the AND gate are HIGH (1)."</h1> |
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+ | <h3 style="text-align:right">©Wikipedia</h3> | ||
<img src="https://static.igem.org/mediawiki/2018/4/44/T--CPU_CHINA--demonstrate-doorclose.jpg" id="doorClose"> | <img src="https://static.igem.org/mediawiki/2018/4/44/T--CPU_CHINA--demonstrate-doorclose.jpg" id="doorClose"> | ||
<img src="https://static.igem.org/mediawiki/2018/5/51/T--CPU_CHINA--demonstrate-dooropen.jpg" id="doorOpen" style="display:none;"> | <img src="https://static.igem.org/mediawiki/2018/5/51/T--CPU_CHINA--demonstrate-dooropen.jpg" id="doorOpen" style="display:none;"> |
Revision as of 04:30, 5 December 2018
"The AND gate is a basic digital logic gate that implements logical conjunction. A HIGH output (1) results only if all the inputs to the AND gate are HIGH (1)."
©Wikipedia
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